There are several known schemes to synchronize on serial data streams of the order of 20 megahertz, but they all have drawbacks. A few of such schemes are: encoding of the serial data stream, such as Miller code, Manchester code, Bi-phase, Return to Zero (RZ), etc.; countdown, using a higher frequency clock and strobing the serial stream to lock-on to a sync bit; and delay lines with taps to clock bits.
The encoding of serial data streams is used to a large degree in radio transmission and magnetic recording. The peripheral circuitry often has certain characteristics which make one coding scheme or another particularly desirable. For instance, the Miller code has a power spectrum for a random serial data stream which peaks at three-eighths of the data rate. This is useful in systems which do not work well at low frequencies. Relative to a Non-Return-to-Zero (NRZ) serial stream, which lacks any coding, the Miller code has five times the power density at its peak frequency than does the NRZ serial stream at that frequency. Similarly, the Manchester code requires about twice the bandwidth of NRZ at the same serial bit rate. Hence, for a random binary data stream, NRZ has the lowest bandwidth requirements. If one wishes to put this serial stream through logic circuitry or long coaxial lines, the low bandwidth requirement of NRZ is a major advantage. Other coding schemes such as Bi-phase and Return-to-Zero (RZ) have even higher bandwidth requirements than the Miller code. (A more extensive coverage of the relative merits of coding schemes is given in an article by Charles F. Spitzer, Computer Design, October 1973, page 83, entitled "Digital Magnetic Recording of Wideband Analog Signals".)
In using an NRZ format for a serial data stream, synchronization can be achieved by sampling the data stream at 4, 8 or 16 times the serial bit rate. When it has been established that a group of bits is coming, a countdown network can then be enabled to clock in the data stream at the bit rate. This approach works very well at low bit rates, a few megahertz or less, but runs into problems of noise, power requirements, and cost when one moves into the 20 megahertz bit rate region. In general, it is wise to keep frequencies low when dealing with silicon integrated logic circuits. The use of the high frequencies can be the cause of many subtle problems.
The state-of-the-art in delay lines has progressed to the point where 50 nanosecond delays can be packaged in sizes very similar and compatible with integrated logic circuits. These delay lines have bandwidths on the order of 50 megahertz which make them useful for certain applications, but the cost is high. Further, use of these delay lines requires additional buffering circuits which complicates design and increases the size of the device.
The factors mentioned attributable to the different synchronization schemes have different relative importance depending on the particular application. In many cases the individual factors of size, bandwidth, cost, power, bit rate, and complexity, etc. may not be important or may be weighed differently.